1. Field of the Invention
This invention relates generally to semiconductor memory circuits, and particularly to circuits and methods for detecting redundant memory data to be used for replacing normal memory data.
2. State of the Art
Semiconductor memories generally include a multitude of memory cells arranged in rows and columns. Each memory cell is structured for storing digital information in the form of a “1” or a “0” bit. Many semiconductor memories include extra, i.e., redundant, memory cells that may be substituted for failing memory cells. Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows or redundant columns in the semiconductor memory.
Conventionally, when a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell's row address is permanently stored (typically in pre-decoded form) by programming nonvolatile elements (e.g., fuses, antifuses, Electrically Programmable Read-Only memory (EPROM), and FLASH memory cells) on the semiconductor memory. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a row address that corresponds to the row address stored on the chip, redundant circuitry in the memory causes access to a redundant row instead of the row identified by the received memory address. Since every memory cell in the failing cell's row has the same row address, the redundant row replaces every cell in the failing cell's row, both operative and failing, with the redundant memory cells in the redundant row.
Similarly, when a redundant column is used to repair the semiconductor memory, the failing cell's column address is permanently stored (typically in pre-decoded form) on the chip by programming nonvolatile elements on the chip. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of, or simultaneously with, the memory cell identified by the received memory address. Since every memory cell in the failing cell's column has the same column address, every cell in the failing cell's column, both operative and failing, is replaced by a redundant memory cell in the redundant column. This process for repairing a semiconductor memory using redundant rows and columns is well known in the art.
Concerning redundant memory columns, various methods exist for selecting whether to use the normal memory column or the redundant memory column. As access times continue to decrease for memory devices, this normal versus redundant selection process for memory columns begins to take up a larger portion of the overall access time from a valid address into the memory array to a valid data signal out of the memory array. Conventionally, redundant memory column selection has involved some sort of multiplexer to select either the data bit pair (BIT and BIT*) from the normal memory column or the data bit pair for the redundant memory column. The multiplexer may occur in various places. In some implementations, the multiplexer may be positioned as directly after the normal and redundant memory columns (i.e., directly attached to the BIT and BIT* signals). In other implementations, a sense amplifier may be connected to the normal memory column and another sense amplifier may be connected to the redundant memory column, with the multiplexer connected to the outputs of the sense amplifiers. In yet other implementations, logic may be implemented to prevent the read cycle from taking place on the normal memory column when the redundant memory column is to be selected in place of the normal memory column. All of these implementations tend to slow the read process down relative to a column read without a redundant memory column. In the multiplexer implementations, the normal data may go through a longer, and therefore slower, logic path including the multiplexer. In addition, decode logic for the multiplexer select signal may be slow. In the normal memory column disabling implementation, the logic required to determine when to disable might add additional time to the read path.
It would be advantageous to provide an apparatus and method for allowing selection of a redundant memory column rather than the normal memory column that does not create any additional delay in the normal memory column access time and enables access times on the redundant memory column that are at least as fast as that for the normal memory column.